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NXP Semiconductors /MIMXRT1062 /USDHC1 /CLK_TUNE_CTRL_STATUS

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Interpret as CLK_TUNE_CTRL_STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DLY_CELL_SET_POST 0DLY_CELL_SET_OUT 0DLY_CELL_SET_PRE 0 (NXT_ERR)NXT_ERR 0TAP_SEL_POST 0TAP_SEL_OUT 0TAP_SEL_PRE0 (PRE_ERR)PRE_ERR

Description

CLK Tuning Control and Status

Fields

DLY_CELL_SET_POST

DLY_CELL_SET_POST
DLY_CELL_SET_OUT

DLY_CELL_SET_OUT
DLY_CELL_SET_PRE

DLY_CELL_SET_PRE
NXT_ERR

NXT_ERR
TAP_SEL_POST

TAP_SEL_POST
TAP_SEL_OUT

TAP_SEL_OUT
TAP_SEL_PRE

TAP_SEL_PRE
PRE_ERR

PRE_ERR

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data